1. Field of the Invention
The present invention relates to a silicon-on-insulator (SOI) device, and more particularly, to a method of making a metal-oxide-semiconductor field-effect-transistor (MOSFET) on a SOI substrate of high threshold voltage and low junction leakage to form a high-performance dynamic random access memory (DRAM) cell.
2. Description of the Prior Art
As the dimensional aspect of devices continue to decrease, the parasitic effects of MOS devices have become a critical factor in both device performance and circuit integrity. Recently, silicon-on-insulator (SOI) substrates, normally formed by a Separation by Implantation Oxygen (SIMOX) method, have been developed as a solution. A metal-oxide-semiconductor field-effect transistor (MOSFET) formed on the SOI substrate is installed in a single crystal layer, and electrically isolated from an underlying silicon substrate by a silicon dioxide isolation layer; the structural layout of the MOSFET thereby prevents the latch up phenomenon of electrical devices and avoids electrical breakdown.
Due to the above advantages, the SOI substrate has been applied to many semiconductor products, such as dynamic random access memory (DRAM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), flash memory, power IC and other consuming IC. However, the gradual increase in the application of the SOI device have created some problems which need to be resolved.
For example, a DRAM unit installed on a SOI substrate is normally biased a pre-selected voltage on the silicon layer of the SOI substrate to control both the threshold voltage (Vt) and sub-threshold voltage of a gate channel. However, the gate channel reaches an undesired floating state during standby mode due to the inability of the conventional SOI to force back-gate bias. This results in limitations in the applications of the SOI device to memory devices. Furthermore, sustaining a high threshold voltage (high Vt) requires the use of a high-dosage Vt adjusting implant process which can lead to high junction leakage and low gate electrode breakage voltage. Also, the use of a large concentration of impurities causes decreased mobility which can reduce the channel performance of a device.
Hitherto, few methods have been proposed to resolve the above-mentioned problems. In U.S. Pat. No. 6,088,260, Choi and Jin Hyeok proposed the use of a SOI substrate to form a DRAM cell. The SOI substrate is provided with a conduction layer for a plate electrode using wafer bonding technology. Choi and Jin Hyeok further utilizes the SOI substrate with the plate electrode to fabricate a DRAM device without a stacked capacitor. Although the method disclosed by Choi and Hyeok produces an improved DRAM device, the above-mentioned problems still need to be resolved.
It is an objective of the present invention to provide a SOI device that is applicable to a DRAM cell by having back-gate control to obtain superior channel control performance and minimum parasitic effects without heavy doping for Vt adjustment.
Another objective of the present invention is to provide a SOI device with high threshold voltage and lower junction leakage on an improved SOI substrate and a method for making the same.
A further objective according to the present invention is to provide a method for making a DRAM unit, possessing high threshold voltage and low junction leakage, on a SOI substrate formed by the SIMOX method.
The SOI device of the present invention comprises a MOS transistor formed on a SOI substrate. The SOI substrate includes a first insulating layer, a first semiconductor layer having a first conductivity type, a second insulating layer, and a second semiconductor layer having a first conductivity type, formed on a substrate, respectively. The MOS transistor includes a gate formed on the second semiconductor layer and a source and drain region, having a second conductivity type, formed on either side of the gate in the second conductive layer. A first and second oxidation region are formed in the first semiconductor layer below the source and the drain, respectively. Both the first and second oxidation regions are contiguous with the second insulating layer.
In another embodiment of the present invention, a SOI DRAM unit comprising a MOS transistor and an improved SOI substrate having back-gate control is provided. The SOI substrate includes a first insulating layer, a back-gate layer having a first conductivity type positioned on the first insulating layer, a second insulating layer, and a silicon layer having a first conductivity type formed on a substrate, respectively.
The MOS transistor includes a gate formed on the silicon layer and a source and drain region, having a second conductivity type, formed on either side of the gate in the silicon layer, wherein the source and the drain electrically connects to a bit line and a capacitor, respectively. A first oxidation region is formed in the back-gate layer below the source and a second oxidation region is formed in the back-gate layer below the drain. Both the first and the second oxidation regions are contiguous with the second insulating layer.